Integrated circuit chips (also referred to as “IC chips” or “chips”) are typically encapsulated into a package, which often includes a ceramic or plastic substrate. Other materials, such as an organic laminate, may be used for the substrate. The substrate provides the package with a mechanical base support and a form of electrical interface that would allow the external world to access devices on the chip housed within the package. The chip package typically attaches to a printed circuit board (PCB).
To increase space utilization, two or more chips may be attached to a PCB in a stacked arrangement. The chip stack is referred to as a three dimensional (3D) package. A chip with the capability of being used in a 3D package, referred to herein as a 3D chip, utilizes through-silicon vias (TSVs), also known as through-substrate vias, to pass electrical signals from one side of the chip to another.
A chip can be attached to a package substrate, to another chip, or even directly to a PCB utilizing C4 (Controlled Collapse Chip Connection) bumps to bond the chip to a substrate or board and provide electrical interconnection. C4 bumps connect input/output (I/O) connection terminals, or contact pads, on the chip to contact pads on the surface it connects to. Typically, a large number of contact pads are disposed in a two dimensional array over a substantial portion of a major surface of the chip (such as in a ball grid array—BGA).
The bumps can be made of solder. After the chip is placed on the connecting surface, the solder is heated and reflowed to form solder joints. This attachment is mechanically strong and reliable in the presence of thermal stresses. However, as the contact pads become smaller and the pitch (the center to center spacing between the contact pads) is reduced, the solder bump sizes are also reduced. As the solder bump size decreases, the solder joints become mechanically and thermally weaker. In addition, the solder ball size defines the standoff distance between the chip and the surface the chip connects to. If the standoff becomes too small, there are increased fatigue stresses on the solder joints during thermal cycling and a greater possibility of undesirable residues remaining in that space and causing degradation.
To obtain better scalability, as well as reduce electromigration concerns, designers sometimes replace C4 bumps made of solder with more defined conductive structures, such as copper pillars or copper pedestals. A copper pillar can be plated onto a contact pad and then solder can be plated onto the copper pillar to make the connection.
With the use of copper pillar bumps, the stresses imposed on the chip, especially during the cool-down from the chip join process, are not as well mitigated as with the use of solder bumps. The high shear stresses caused by the CTE (coefficient of thermal expansion) mismatch between the chip and a laminate, now connected by a more rigid conductive structure, results in a higher probability of C4 interconnection defects (i.e., small cracks or voids in the chip metallurgy under C4 bumps).
To maintain a rigid contact structure that would both allow for reduced pitch and minimize strains in the interconnection, portions of TSVs embedded in a semiconductor substrate may be exposed to form protruding contact pads or pillars, which may then be used in interconnecting the substrate. This is often used in the case of a silicon interposer, where a substrate acts as an intermediate layer used for interconnection routing or as a ground/power plane. A silicon interposer may itself be considered an integrated circuit chip. A silicon interposer may also have an intermediate CTE somewhere between a chip and the PCB the interposer connects the chip to. However, this technology need not be limited to interposers, and 3D chips that have devices may also utilize embedded TSVs in this manner.